1. Field of the Invention
The present invention relates to a semiconductor device including a reference voltage circuit such as a voltage detector (hereinafter referred to as VD) or a voltage regulator (hereinafter referred to as VR).
2. Description of the Related Art
FIG. 18 is a schematic cross sectional view of a reference voltage circuit of a conventional semiconductor device, and FIG. 4 is a circuit diagram of the reference voltage circuit. The reference voltage circuit is a circuit for always outputting a constant voltage with respect to the potential of a low voltage supply terminal from an output terminal irrespective of a voltage applied to a high voltage supply terminal.
The reference voltage circuit is constituted of an enhancement type (hereinafter referred to as E-type) N-channel MOS (hereinafter referred to as NMOS) and a depletion type (hereinafter referred to as D-type) NMOS in series connection. In the E-type NMOS, a gate and a drain are short-circuited with each other, and a source is connected to the low voltage supply terminal. In the D-type NMOS, a source and a gate are connected to each other, and a drain is connected to the high voltage supply terminal. The drain of the E-type NMOS and the source of the D-type NMOS are connected with each other, and the output terminal is provided thereto.
In the above-described reference voltage circuit of the conventional semiconductor device, N+polycrystalline silicon is used for the polarities of the gate electrodes of the E-type NMOS and the D-type NMOS as shown in FIG. 18 because of the easiness of manufacture and the stability. in this case, the E-type is a surface channel and the D-type is a buried channel based on the relationship of working function between a gate and a well. The small change of an output voltage to the temperature change is given as important characteristics of the reference voltage circuit. However, the threshold voltage of MOS and the degree of the change to the temperature change of mutual conductance largely differ between the surface channel and the buried channel. As a result, there is a problem in that it is difficult to make the change of the output voltage to the temperature change smaller.
The present invention has been made in view of the above, and an object of the present invention is therefore to provide a reference voltage circuit with small fluctuation of an output voltage to a change of temperature and a method of manufacturing the same.
In order to solve the above-described problem, the present invention uses the following means.
(1)
There is provided a semiconductor device comprising a reference voltage circuit in which a gate and a drain of an enhancement MOS transistor of one conductivity type in which the gate and the drain are short-circuited are connected to a gate and a source of a depletion MOS transistor of one conductivity type in which the gate and the source are short-circuited and a connection point thereof is used as an output node, characterized in that a polarity of a gate electrode of the enhancement MOS transistor of one conductivity type is opposite conductivity type and a polarity of a gate electrode of the depletion MOS transistor of one conductivity type is one conductivity type.
(2)
There is provided a semiconductor device comprising a reference voltage circuit in which a source of an enhancement MOS transistor of one conductivity type in which a gate and a drain are short-circuited is connected to a drain of a depletion MOS transistor of one conductivity type in which a gate and a source are short-circuited and a connection point thereof is used as an output node, characterized in that a polarity of a gate electrode of the enhancement MOS transistor of one conductivity type is opposite conductivity type and a polarity of a gate electrode of the depletion MOS transistor of one conductivity type is one conductivity type.
(3)
There is provided a semiconductor device comprising a reference voltage circuit in which a gate and a drain of an enhancement MOS transistor of one conductivity type in which the gate and the drain are short-circuited are connected to a source of a depletion MOS transistor of one conductivity type in which a gate is short-circuited with a source of the enhancement MOS transistor of one conductivity type and a connection point thereof is used as an output node, characterized in that a polarity of a gate electrode of the enhancement MOS transistor of one conductivity type is opposite conductivity type and a polarity of a gate electrode of the depletion MOS transistor of one conductivity type is one conductivity type.
(4)
There is provided a semiconductor device comprising a reference voltage circuit in which a drain of a depletion MOS transistor of one conductivity type in which a gate and a source are short-circuited is connected to a drain and a gate of a first enhancement MOS transistor of opposite conductivity type in which a source is connected to a power supply, a drain of a second enhancement MOS transistor of opposite conductivity type in which a source is connected to the power supply and a gate is connected commonly with the first enhancement MOS transistor of opposite conductivity type is connected to a gate and a drain of an enhancement MOS transistor of one conductivity type in which the gate and the drain are short-circuited, and a connection point thereof is used as an output node, characterized in that a polarity of a gate electrode of the enhancement MOS transistor of one conductivity type is opposite conductivity type and a polarity of a gate electrode of the depletion MOS transistor of one conductivity type is one conductivity type.
(5)
There is provided a semiconductor device comprising a reference voltage circuit in which a drain of a first depletion MOS transistor of one conductivity type in which a gate and a source are short-circuited is connected to a gate and a source of a second depletion MOS transistor of one conductivity type in which the gate and the source are short-circuited, a drain of the second depletion MOS transistor of one conductivity type is connected to a power supply, the source of the first depletion MOS transistor of one conductivity type is connected to an enhancement MOS transistor of one conductivity type in which a gate and a drain are short-circuited, and a connection point thereof is used as an output node, characterized in that a polarity of a gate electrode of the enhancement MOS transistor of one conductivity type is opposite conductivity type and polarities of gate electrodes of the first depletion MOS transistor of one conductivity type and the second depletion MOS transistor of one conductivity type are one conductivity type.
(6)
There is provided a semiconductor device comprising a reference voltage circuit in which a gate and a drain of an enhancement MOS transistor of one conductivity type in which the gate and the drain are short-circuited are connected to a source of a first depletion MOS transistor of one conductivity type in which a gate is short-circuited with a source of the enhancement MOS transistor of one conductivity type, a drain of the first depletion MOS transistor of one conductivity type is connected to a gate and a source of a second depletion MOS transistor of one conductivity type in which the gate and the source are short-circuited, a drain of the second depletion MOS transistor of one conductivity type is connected to a power supply, and a connection point of the drain of the enhancement MOS transistor of one conductivity type and the source of the first depletion MOS transistor of one conductivity type is used as an output node, characterized in that a polarity of a gate electrode of the enhancement MOS transistor of one conductivity type is opposite conductivity type and polarities of gate electrodes of the first depletion MOS transistor of one conductivity type and the second depletion MOS transistor of one conductivity type are one conductivity type.
(7)
There is provided a semiconductor device, characterized in that the gates of the enhancement MOS transistor of one conductivity type and the depletion MOS transistor of one conductivity type are formed of polycrystalline silicon.
(8)
There is provided a semiconductor device, characterized in that the gates of the enhancement MOS transistor of one conductivity type and the depletion MOS transistor of one conductivity type are formed of a lamination structure of polycrystalline silicon and high melting point metal silicide.
(9)
There is provided a semiconductor device, characterized in that polarities of gate electrodes of the first enhancement MOS transistor of opposite conductivity type and the second enhancement MOS transistor of opposite conductivity type are opposite conductivity type.
(10)
There is provided a method of manufacturing a semiconductor device, characterized by comprising the steps of:
forming an element isolating region on a semiconductor substrate;
forming a gate insulating film on the semiconductor substrate;
doping an impurity into the semiconductor substrate for threshold control;
forming a polycrystalline silicon film on the semiconductor substrate;
selectively forming a region of one conductivity type at high concentration in the polycrystalline silicon film;
selectively forming a region of opposite conductivity type at high concentration in the polycrystalline silicon film;
forming an insulating film on the polycrystalline silicon film;
patterning the insulating film and the polycrystalline silicon film to form a gate electrode; and
forming regions to be a source and a drain of a MOS transistor.
(11)
There is provided a method of manufacturing a semiconductor device, characterized by comprising the steps of:
forming an element isolating region on a semiconductor substrate;
forming a gate insulating film on the semiconductor substrate;
doping an impurity into the semiconductor substrate for threshold control;
forming a polycrystalline silicon film on the semiconductor substrate;
selectively forming a region of one conductivity type at high concentration in the polycrystalline silicon film;
selectively forming a region of opposite conductivity type at high concentration in the polycrystalline silicon film;
forming high melting point metal silicide on the polycrystalline silicon film;
forming an insulating film on the high melting point metal silicide;
patterning the insulating film, the high melting point metal silicide and the polycrystalline silicon film to form a gate electrode; and
forming regions to be a source and a drain of a MOS transistor.
(12)
There is provided a method of manufacturing a semiconductor device, characterized in that the step of doping an impurity for threshold control is conducted by an ion injection method, and the impurity has the same conductivity type as a MOS transistor.
(13)
There is provided a method of manufacturing a semiconductor device, characterized in that the insulating film is a silicon oxide film formed by a chemical vapor deposition method or a thermal oxidization method, and the thickness of the insulating film is in a range of 1000 xc3x85 to 2000 xc3x85.
(14)
There is provided a method of manufacturing a semiconductor device, characterized in that the insulating film is a silicon nitride film formed by a chemical vapor deposition method, and the thickness of the insulating film is in a range of 1000 xc3x85 to 2000 xc3x85.
(15)
There is provided a method of manufacturing a semiconductor device, characterized in that the high melting point metal silicide is one of molybdenum silicide, tungsten silicide, titanium silicide and platinum silicide and is formed by a chemical vapor deposition method or a sputtering method.
(16)
There is provided a method of manufacturing a semiconductor device, characterized in that the high melting point metal silicide is a substance in which cobalt or titanium formed on the polycrystalline silicon by a sputtering method is silicified.